代码搜索:Key
找到约 10,000 项符合「Key」的源代码
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www.eeworm.com/read/161070/10456820
v key2.v
module key2 (keyin,ledout);
input [7:0] keyin;
output [7:0] ledout;
reg [7:0] ledout_reg;
reg [7:0] buffer;
always @ (keyin)
begin
buffer=keyin;
case(buffer)
8'b11111110:ledout_reg=8'b1
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bld key2.bld
Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -dd f:/dp_fpga/dp-fpga/xc2s100/key/_ngo -nt timestamp -p
xc2s100-pq208-5 key2.ngc k
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pad key1.pad
Release 4.1WP3.x - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
Mon Feb 17 16:03:37 2003
Xilinx PAD Specification File
*****************************
Input file: par_tem
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bgn key1.bgn
Release 4.1WP3.x - Bitgen E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
Loading design for application Bitgen from file key1.ncd.
"key1" is an NCD, version 2.36, device xc2s100,
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_prj key1._prj
insert `timescale 1ns/1ns
include
include key1.v
include d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v
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bit key2.bit
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dly key2.dly
Release 4.1WP3.x - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
Mon Feb 17 16:05:02 2003
File: key2.dly
The 20 Worst Net Delays are:
-------------------------------
| Max De
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pad key2.pad
Release 4.1WP3.x - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
Mon Feb 17 16:05:02 2003
Xilinx PAD Specification File
*****************************
Input file: par_tem