代码搜索:Interface
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h mb_interface.h
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE
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cpp calculate_interface.cpp
#include "calculate_interface.h"
/*
* Implementation of interface class CalculateInterface
*/
CalculateInterface::CalculateInterface(const QString &service, const QString &path, const QDBusConnec
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h calculate_interface.h
#ifndef CALCULATE_INTERFACE_H_1185933162
#define CALCULATE_INTERFACE_H_1185933162
#include
#include
#include
#include
#include
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srr uc_interface.srr
$ Start of Compile
#Mon Jul 19 18:36:03 2004
Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
VHDL syntax chec
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edf uc_interface.edf
(edif (rename uc_interface "uC_interface")
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2004 7 19 18 36 4)
(author "Synpli
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plg uc_interface.plg
@P: Worst Slack : 989.769
@P: clk - Estimated Frequency : 97.7 MHz
@P: clk - Requested Frequency : 1.0 MHz
@P: clk - Estimated Period : 10.231
@P: clk - Requested Period : 1000.000
@P: clk
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ncf uc_interface.ncf
#
# Constraints generated by Synplify Pro 7.1, Build 152R
#
# Period Constraints
#Begin clock constraints
#End clock constraints
# Output Constraints
# Input Constraints
# Location Con