代码搜索:Input0

找到约 54 项符合「Input0」的源代码

代码结果 54
www.eeworm.com/read/177415/9456060

c drv_key.c

/******************************************************************************************************** * * Copyright (C) SEIKO EPSON CORP. 2002 * * File name: Drv_key.c * T
www.eeworm.com/read/464665/7067334

asp createfawq.asp

www.eeworm.com/read/413476/11154465

ez tesk500.ez

;p10 key1 Non_Auto motor run ;p11 key2 Auto motor run ;p12 key3 Non_Auto motor run duty+ ;p13 key4 Non_Auto motor run duty- ; ;p30 motor ; [device] snc539 [key] direct=1 debounce=2 ;1
www.eeworm.com/read/413456/11155141

ez test56.ez

[device] sn56085 [key] scan=48 [files] a.wav b.wav c.wav d.wav e.wav f.wav g.wav h.wav i.wav j.wav k.wav l.wav m.wav n.wav o.wav p.wav q.wav r.wav s.wav t.wav u.wav v.wav w.
www.eeworm.com/read/217320/14969265

txt readme.txt

EC51712GPIOTEST 测试程序使用说明 1.读测试 点击[Read]按钮,在该按钮的左边的灰色编辑框中会显示读到的值,该值为十进制值,首先将它转化为八位的二进制值,低四位即对应四个输入GPIO的值,为1即表示对应GPIO管脚为高电平,为'0'即表示对应GPIO管脚为低电平,对应关系为: Bit0 对应 <mark>Input0</mark> ...
www.eeworm.com/read/413477/11154413

ez tesk21k.ez

;p10 key1 Non_Auto motor run ;p11 key2 Auto motor run ;p12 key3 Non_Auto motor run duty+ ;p13 key4 Non_Auto motor run duty- ; ;p30 motor ; [device] snc21085 [key] direct=4 debounce=2
www.eeworm.com/read/422532/10631535

vhd condsig.vhd

-- MAX+plus II VHDL Example -- Conditional Signal Assignment -- Copyright (c) 1994 Altera Corporation ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT ); E
www.eeworm.com/read/159105/10694571

vhd condsig.vhd

-- MAX+plus II VHDL Example -- Conditional Signal Assignment -- Copyright (c) 1994 Altera Corporation ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT ); E
www.eeworm.com/read/399935/7821170

vhd condsig.vhd

-- MAX+plus II VHDL Example -- Conditional Signal Assignment -- Copyright (c) 1994 Altera Corporation ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT ); E
www.eeworm.com/read/126327/14428574

vhd condsig.vhd

-- MAX+plus II VHDL Example -- Conditional Signal Assignment -- Copyright (c) 1994 Altera Corporation ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT ); E