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alarm_clock.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
dssensitivity.m
function [euncraw,euncnorm, euncquot]=dssensitivity(x, parnums, fhandle, uncfn, mcIT, pinch_samples, pinch_type)
%=========================================================================
% dssen
tv.h
// tv.h -- Tv and Remote classes
#ifndef TV_H_
#define TV_H_
class Tv
{
public:
friend class Remote; // Remote can access Tv private parts
enum {Off, On};
enum {MinVal,MaxVal =
de2_ccd_pip.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
rate_adjust.fit.eqn
--A1L25 is always0~163 at LC9
A1L25_or_out = Rate_Set[8];
A1L25 = Rate_Data[8] $ A1L25_or_out;
--A1L35 is always0~167 at LC10
A1L35_or_out = Rate_Set[9];
A1L35 = Rate_Data[9] $ A1L35_or_out;
watermethod.cpp
// Watermethod.cpp: implementation of the CWatermethod class.
//
//////////////////////////////////////////////////////////////////////
#include "stdafx.h"
#include "DCTWater.h"
#include "Water
dff1.map.eqn
--A1L72Q is qout[7]~reg0
--operation mode is normal
A1L72Q_lut_out = din[7];
A1L72Q = DFFEA(A1L72Q_lut_out, clk, !r, , , , );
--A1L52Q is qout[6]~reg0
--operation mode is normal
A1L52Q_l
spi_bitcounter_rtl.v
// HDLi Version 3.0d IP Bundle 1999.08.25
// Parameters: counter -b6 -t0 -p1 -f0 -L0 -C -c -R -S -M -l vsc983 -padlib vst8p31 -Synopsys -rtl -nentity -nadd_p -ntiming -nls -verilog -br 0,4,8,12,32
spi_bytecounter_rtl.v
// HDLi Version 3.0 (beta)
// Parameters: counter -b8 -t0 -p1 -f0 -L0 -C -c -R -S -M -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0
// spi_bytecounter: 126.00 phy