代码搜索:Inference

找到约 1,820 项符合「Inference」的源代码

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vhd latchinf.vhd

-- MAX+plus II VHDL Example -- Latch Inference -- Copyright (c) 1994 Altera Corporation ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT ); END latchinf; ARCHITECTU
www.eeworm.com/read/159105/10694411

vhd counters.vhd

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear
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vhd latchinf.vhd

-- MAX+plus II VHDL Example -- Latch Inference -- Copyright (c) 1994 Altera Corporation ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT ); END latchinf; ARCHITECTU
www.eeworm.com/read/399935/7821166

vhd counters.vhd

-- MAX+plus II VHDL Example -- Efficient Counter Inference -- Copyright (c) 1994 Altera Corporation ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear
www.eeworm.com/read/399935/7821202

vhd latchinf.vhd

-- MAX+plus II VHDL Example -- Latch Inference -- Copyright (c) 1994 Altera Corporation ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT ); END latchinf; ARCHITECTU
www.eeworm.com/read/136697/13365348

m apsumhei.m

function bs = apsumhei(FAMbank,Aj,moments,areas) % bs = apsumhei(FAMbank,Aj,moments,areas) % % Algebraic-product operator for the inference. Summation of the outputs. % Defuzzification with HEIGHT m
www.eeworm.com/read/136697/13365421

m inferenc.m

function Bs = inferenc(A,B,FAMbank,infop) % Bs = inferenc(A,B,FAMbank,infop) % % With Bj and aj and the inference operator infop Bj*=infop(aj,Bj) is % calculated. Bj* is the fuzzy conclusion for the
www.eeworm.com/read/140847/5779740

readme

% Stable conditional Gaussian inference % Written by Rainer Deventer @techreport{Lauritzen99, author = "S. Lauritzen and F. Jensen", title = "Stable Local Computation with Conditional {G}aussian
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readme

% Stable conditional Gaussian inference % Written by Rainer Deventer @techreport{Lauritzen99, author = "S. Lauritzen and F. Jensen", title = "Stable Local Computation with Conditional {G}aussian
www.eeworm.com/read/487590/6506065

vhd t155.vhd

-- -- This file implements Register inference on variables in clock processes. -- The variable TMP is read before beeing assigned to hence, infers a flip-flop. -- Note: Q will also be a flip-flop (