代码搜索：Inference

找到约 1,820 项符合「Inference」的源代码

代码结果 1,820
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/343627/3218106

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\RAM\V2BRAM_READ_FIRST\proj.prj #-- Written on Thu Feb 14 16:08:44 2002 #add_file options
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www.eeworm.com/read/343627/3218108

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\RAM\V2BRAM_WRITE_FIRST\proj.prj #-- Written on Thu Feb 14 16:09:52 2002 #add_file options
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www.eeworm.com/read/343627/3218124

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\MULT18X18S_INSTANCIATE\proj.prj #-- Written on Thu Feb 14 16:07:00 2002 #add_file options
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www.eeworm.com/read/343627/3218133

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VHDL\SRL_DYNAMIC\proj.prj #-- Written on Thu Feb 14 16:39:25 2002 #add_file options add_file -vh
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www.eeworm.com/read/343627/3218137

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VHDL\SRL_STATIC\proj.prj #-- Written on Thu Feb 14 16:40:16 2002 #add_file options add_file -vhd
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www.eeworm.com/read/343627/3218166

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VHDL\RAM\V2BRAM_NO_CHANGE\proj.prj #-- Written on Thu Feb 14 16:36:49 2002 #add_file options add
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www.eeworm.com/read/343627/3218170

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VHDL\RAM\V2BRAM_WRITE_FIRST\proj.prj #-- Written on Thu Feb 14 16:37:52 2002 #add_file options a
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www.eeworm.com/read/343627/3218176

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VHDL\MULT18X18S_INSTANCIATE\proj.prj #-- Written on Thu Feb 14 16:35:24 2002 #add_file options a
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www.eeworm.com/read/393024/2489892

vhd configram.vhd

-- Only XST supports RAM inference -- Infers Single Port Block Ram library IEEE; use IEEE.STD_LOGIC_1164.all; -- defines std_logic types use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL
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www.eeworm.com/read/154079/5642592

prj proj.prj

#-- Synplicity, Inc. #-- Version 7.0.3 #-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\RAM\V2BRAM_READ_FIRST\proj.prj #-- Written on Thu Feb 14 16:08:44 2002 #add_file options
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