代码搜索：Inference
找到约 1,820 项符合「Inference」的源代码
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www.eeworm.com/read/415351/11075445
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/415351/11075465
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/415351/11075519
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/415351/11075594
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/268989/11112296
v 计数器.v
// Efficient Counter Inference
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, enable, up_down,
qa, qb, qc, qd, qe, qf, qg,
qh, qi, qj,
www.eeworm.com/read/136696/13365600
m kosko.m
function [dbp,W]=kosko(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p)
% KOSKO: When the inputs of fuzzy inference systems are crisp rather than
% fuzzy value, decision process becomes simpler. This function
www.eeworm.com/read/343627/3218087
prj proj.prj
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\ROM\DEFAULT\proj.prj
#-- Written on Thu Feb 14 16:10:30 2002
#add_file options
add_file
www.eeworm.com/read/343627/3218098
prj proj.prj
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\DCM_INSTANCIATE\PHASE_SHIFTING\proj.prj
#-- Written on Thu Feb 14 15:56:05 2002
#add_file
www.eeworm.com/read/343627/3218111
prj proj.prj
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\RAM\DEFAULT\proj.prj
#-- Written on Thu Feb 14 16:07:34 2002
#add_file options
add_file
www.eeworm.com/read/343627/3218121
prj proj.prj
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\XROADS\INFERENCE_STATUS\SPRO_703\VERILOG\DCM\proj.prj
#-- Written on Thu Feb 14 14:58:48 2002
#add_file options
add_file -verilog