代码搜索：Inference
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www.eeworm.com/read/305986/13755614
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/305054/13779379
txt 各种功能的计数器.vhd.txt
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/305054/13779380
txt 带load、clr等功能的寄存器.vhd.txt
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/140847/5779179
m online1.m
% Check that online inference gives same results as filtering for various algorithms
N = 3;
Q = 2;
ss = N*2;
rand('state', 0);
randn('state', 0);
obs_size = 1;
discrete_obs = 0;
bnet = mk_chmm(N,
www.eeworm.com/read/140847/5779428
m hmm_2tbn_inf_engine.m
function engine = hmm_2TBN_inf_engine(bnet, varargin)
% HMM_2TBN_INF_ENGINE Inference engine for DBNs which uses the forwards-backwards algorithm.
% engine = hmm_2TBN_inf_engine(bnet, ...)
%
% The DBN
www.eeworm.com/read/133943/5897363
m online1.m
% Check that online inference gives same results as filtering for various algorithms
N = 3;
Q = 2;
ss = N*2;
rand('state', 0);
randn('state', 0);
obs_size = 1;
discrete_obs = 0;
bnet = mk_chmm(N,
www.eeworm.com/read/133943/5897611
m hmm_2tbn_inf_engine.m
function engine = hmm_2TBN_inf_engine(bnet, varargin)
% HMM_2TBN_INF_ENGINE Inference engine for DBNs which uses the forwards-backwards algorithm.
% engine = hmm_2TBN_inf_engine(bnet, ...)
%
% The DBN
www.eeworm.com/read/382666/6286480
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/382666/6286504
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/494695/6360541
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all