代码搜索：Inference
找到约 1,820 项符合「Inference」的源代码
代码结果 1,820
www.eeworm.com/read/324303/13273863
m bay_lssvm.m
function [A,B,C,D,E] = bay_lssvm(model,level,type, nb, bay)
% Compute the posterior cost for the 3 levels in Bayesian inference
%
% >> cost = bay_lssvm({X,Y,type,gam,sig2}, level, type)
% >> cost = b
www.eeworm.com/read/136696/13365617
m mamdani.m
function [dbp,W]=mamdani(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o)
%MAMDANI: When the inputs of fuzzy inference systems are crisp rather than
% fuzzy value, decision process becomes simpler. This function
www.eeworm.com/read/136696/13365629
m larsen.m
function [dbp,W]=larsen(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o)
%LARSEN: When the inputs of fuzzy inference systems are crisp rather than
% fuzzy value, decision process becomes simpler. This function
%
www.eeworm.com/read/319921/13439510
txt 带load、clr等功能的寄存器.txt
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/319921/13439538
txt 各种功能的计数器.txt
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/318947/13466018
m bay_lssvm.m
function [A,B,C,D,E] = bay_lssvm(model,level,type, nb, bay)
% Compute the posterior cost for the 3 levels in Bayesian inference
%
% >> cost = bay_lssvm({X,Y,type,gam,sig2}, level, type)
% >> cost = b
www.eeworm.com/read/316944/13514056
m bay_lssvm.m
function [A,B,C,D,E] = bay_lssvm(model,level,type, nb, bay)
% Compute the posterior cost for the 3 levels in Bayesian inference
%
% >> cost = bay_lssvm({X,Y,type,gam,sig2}, level, type)
% >> cost = b
www.eeworm.com/read/312754/13605419
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/312754/13605443
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/305986/13755590
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all