代码搜索：Inference
找到约 1,820 项符合「Inference」的源代码
代码结果 1,820
www.eeworm.com/read/263314/11367751
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/157209/11730192
txt 简单的锁存器.txt
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/344239/11895955
java tuple.java
//: net/mindview/util/Tuple.java
// Tuple library using type argument inference.
package net.mindview.util;
public class Tuple {
public static TwoTuple tuple(A a, B b) {
return
www.eeworm.com/read/338523/12299761
bak invp_flc.bak
/*
* File : fuzzy_controller.c
*
* An example of Fuzzy Inference System,
* uk = fuzzy_controller(ek, dek)
*
* Written by Chou, Penchen, Aug. 3,2001
* EE Dept., Da-Yeh Univer
www.eeworm.com/read/338523/12300510
c flc_invp.c
/*
* File : flc_invp.c
* Abstract:
* An example C-file S-function for linking Fuzzy Inference System,
* uk = fuzzy_controller(ek, dek)
*
* See simulink/src/sfuntmpl_doc.c
*
www.eeworm.com/read/338238/12317176
h loggbp.h
#include "GBP.h"
#include
#include
#ifndef __LOG_GENERALIZED_BP__
#define __LOG_GENERALIZED_BP__
class LogGBP : public GBP {
/**
This class makes inference using Jonathan Y
www.eeworm.com/read/149607/12362871
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/227189/14437608
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/125701/14470245
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/251838/4414425
m scg3.m
% Compare various inference engines on the following network (from Jensen (1996) p84 fig 4.17)
% 1
% / | \
% 2 3 4
% | | |
% 5 6 7
% \/ \/
% 8 9
% where all arcs point downwards
N = 9;