代码搜索：Inference
找到约 1,820 项符合「Inference」的源代码
代码结果 1,820
www.eeworm.com/read/199789/7822600
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/198238/7946370
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/198238/7946459
txt 简单的锁存器.txt
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/197597/7984766
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/145313/12736141
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/246188/12752180
+=
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/145129/12752292
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/145059/12754594
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/141282/13024741
txt 带load、clr等功能的寄存器.txt
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/325023/13231610
java tuple.java
//: net/mindview/util/Tuple.java
// Tuple library using type argument inference.
package net.mindview.util;
public class Tuple {
public static TwoTuple tuple(A a, B b) {
return