代码搜索：FSM
找到约 3,748 项符合「FSM」的源代码
代码结果 3,748
www.eeworm.com/read/379202/9204664
fsm fsmviewer.fsm
fsm_options -device {STATE[0:9]}
define_state stopon1 0000000001 {e:\my synplyfy\lift\flift.vhd} 47 2 47 17
state_output stopon1 {STATE[9]} 1
define_state dooropen 0000000010 {e:\my synplyfy\li
www.eeworm.com/read/378479/9229907
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/374228/9415545
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/177261/9462727
c fsm.c
/* fsm.c - {Link, IP} Control Protocol Finite State Machine */
/* Copyright 1995 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
* Copyright (c) 1989 Carnegie Mellon University.
* All ri
www.eeworm.com/read/372505/9507744
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/371315/9556460
h fsm.h
/*
* fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
*
* Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
*
* Redistribution and use in source and bi
www.eeworm.com/read/371315/9556538
c fsm.c
/*
* fsm.c - {Link, IP} Control Protocol Finite State Machine.
*
* Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
*
* Redistribution and use in source and binary forms,
www.eeworm.com/read/169221/9875091
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/168934/9887663
c fsm.c
/* fsm.c - {Link, IP} Control Protocol Finite State Machine */
/* Copyright 1995 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
* Copyright (c) 1989 Carnegie Mellon University.
* All ri
www.eeworm.com/read/168252/9927334
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta