代码搜索：FPGA EDK

找到约 10,000 项符合「FPGA EDK」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/190958/5170177

hdlsourcefiles isim.hdlsourcefiles

C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab1/Flow_Lab/INT_TEST.VHD J:/I.27/rtf/vhdl/src/unisims/unisim_VITAL.vhd C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga
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www.eeworm.com/read/346575/3181548

txt savedindexnames.txt

D:\fpga_work\sd_de1\DE2_CCD_CV\software\.metadata\.plugins\org.eclipse.cdt.core\481861272.index D:\fpga_work\sd_de1\DE2_CCD_CV\software\.metadata\.plugins\org.eclipse.cdt.core\3748836039.index
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www.eeworm.com/read/303808/3807059

entries

/Makefile/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /config.mk/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.c/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.h/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /quantum.c/
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www.eeworm.com/read/440835/1787452

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol
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www.eeworm.com/read/440835/1787455

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -w -intstyle ise -ol std -t 1 DDR_TX_TEST_map.ncd DDR_TX_TE
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www.eeworm.com/read/440818/1787493

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high
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_info

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 w1131032666 FE:/farsight_fpga_course/
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www.eeworm.com/read/427629/1969131

_info

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 dE:\farsight_fpga_course\code\high\on
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www.eeworm.com/read/427629/1969252

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/ram_control.v source_file = 1
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www.eeworm.com/read/355352/3054573

ref hdpdeps.ref

V3 3 FL D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd 2008/08/22.14:26:02 I.24 EN work/usbtest 1220499205 FL D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd \ PB ieee/std_logic_1164 1131108373 PB ieee/
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