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FPGA 的代码
spi.txt
module SPI_slave(clk, SCK, MOSI, MISO, SSEL, LED);
input clk;
input SCK, SSEL, MOSI;
output MISO;
output LED;
// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr; always @(po
multiplexer_ifelse.txt
--Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
conversion_altera.vhd
-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE i
counter_nbit.txt
-- n-Bit Synchronous Counter
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(
tcounter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
cl
ram256x8_altera.v
// MAX+plus II Verilog Example
// LPM RAM Instantiation
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module ram256x8 ( data, address, we, inclock,
counter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tp
计数器：generic语句的应用.txt
-- n-Bit Synchronous Counter
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(
多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
多路选择器（使用if－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d: