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三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
tcounter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
cl
ram256x8_altera.v
// MAX+plus II Verilog Example
// LPM RAM Instantiation
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module ram256x8 ( data, address, we, inclock,
counter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tp
多路选择器when.txt
--Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
多路选择器if else.txt
--Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
多路选择器select.txt
--Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
多路选择器when.txt
--Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d: