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FPGA 的代码
moore2.vhd
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
speak.rpt
Project Information d:\fpga\cpld\speak\speak.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/20/2007 15:28:08
Copyright (C) 1988-2002 Al
ps2.vhd
-- The FPGA-evb-S2 Xilinx Spartan-II evaluation board example
--
-- This example reads scan codes from a PS/2 keyboard and
-- displays them on LEDs.
--
-- (C)2001 Jan Pech, j.pech@sh.cvut.cz
entries
/flash.c/1.1.1.1/Thu Nov 2 14:15:01 2006//
/fpga.c/1.1.1.1/Thu Nov 2 14:15:01 2006//
/pci.c/1.1.1.1/Thu Nov 2 14:15:01 2006//
D
program.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\vhdl\l