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FPGA 的代码
莫爾形狀態機1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
莫尔型状态机.vhd
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
t_compact.timesim_vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:54:53 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
t_divider.timesim_vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:58:04 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
t_divider.vhw
-- D:\FPGA\仿真\DIVIDER_定点除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:59:57 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst: