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FPGA 的代码
mealy1 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
i2cslave.v
// Example of I2C slave with 8-bits IO extender
// (c) 2005, 2008 fpga4fun.com, KNJN LLC
// Please define one of these before starting synthesis
//`define Xilinx
//`define Altera
`define Altera
简单的12位寄存器.vhd
-- User-Defined Macrofunction
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk :
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
莫爾形狀態機2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst: