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FPGA 的代码
pelian_contrller.txt
-- Pelican Crossing Controller
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity pelcross is
port(clock, reset, pedestrian : in std_logic;
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad