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FPGA 的代码
usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo_fpga1280x8 is
port(
DATA : in vl_logic_vector(7 downto 0);
DATAOUT : out vl_logic_vector(15 downto
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
scrdrv.c
/*
* \brief DOpE screen driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo_fpga1280x8 is
port(
DATA : in vl_logic_vector(7 downto 0);
DATAOUT : out vl_logic_vector(15 downto
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi