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FPGA 的代码
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
-
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
getpcmdata.tcl
########## Tcl recorder starts at 06/17/08 14:52:44 ##########
set version "7.0"
set proj_dir "D:/CPLD/FPGA"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $pver {_}
pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
bidir.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi