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FPGA 的代码
双向总线.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
双向总线.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
˫
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
dds_srr.htm
#Build: Synplify Pro 9.0.1, Build 024R, Nov 13 2007
#install: C:\Program Files\Synplicity\fpga_901
#OS: Windows XP 5.1
#Hostname: QIN
#Implementation:
˫
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
compile.cfg
[View]
Entity=
Architecture=
TopLevelType=
[file:.\src\readme.txt]
File Time Hi=29639210
File Time Lo=330723840
Enabled=1
[file:.\src\Fpga.bde]
File Time Hi=29639210
File Time Lo=330723840
pci_arbiter_readme.txt
fpga reference design
Offer:QuickLogic
PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixtur
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi