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/* * FPGALUTMapping.java * * Created on 17 July 2003, 20:34 */ package jaga.pj.circuits.fpgaft; import jaga.BitSet; import jaga.pj.circuits.*; /** FPGA LUT Structure is composed of CLBs cont

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

########## Tcl recorder starts at 06/14/07 20:28:55 ########## set version "6.1" set proj_dir "D:/FPGA/VideoGenerator" cd $proj_dir # Get directory paths set pver $version regsub -all {\.}

#-- Synplicity, Inc. #-- Version Synplify for Lattice 8.6.2B #-- Project file d:\fpga\VIDEOG~1\VIDEOG~1.prd #-- Written on Mon Jun 18 08:11:32 2007 # ### Watch Implementation type ### # watch