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FPGA 的代码
简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
条件赋值：使用列举类型.vhd
-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LU
简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
一个简单的状态机.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存儲器舉例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
ch04.7.htm
4.7 FPGA Economics