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FPGA 的代码
fpga_port.v
module FPGA_BUS_PORT(clk,cs,wr,rd,data,add,reg1_out,reg2_out,
clk_out,cs1,wave_out1,DA_clk_out,DA_sleep_out);
input clk,cs,wr,rd;
inout[15:0] data;
input[7:0] add;
output[15:0] reg1_out,reg2
fpga_am.cdf
/* Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP1C3T144) Path("J:/FPGA/my_exercises
fpga_am.pin
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
fpga_am.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
fpga_am.qpf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu