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FPGA 的代码
条件赋值：使用列举类型.vhd
-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LU
generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
cpu_system.txt
-- Structural description of a Microprocessor System
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY cpudemo IS
END cpudemo;
ARCHITECTUR
statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
条件赋值：使用列举类型.txt
-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LU
简单的锁存器.txt
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
dynram.tdf
TITLE "DRAM Controller with Refresh (CAS before RAS) and DTACK Generation" ;
-- Version 1.1, 03.02.1998
-- Copyright Frank Rodler
-- You can download it from www.fpga.com.cn or www.pld.com.cn
PA
statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
cpu_system.txt
-- Structural description of a Microprocessor System
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY cpudemo IS
END cpudemo;
ARCHITECTUR
generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d