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FPGA 的代码
stubi.vhd
-- Generated PORTMAP Stub File: Created by Capture FPGA Flow
-- Matches PCB component pinout with simulation model
-- Created Wednesday, May 13, 2009 08:10:07 中国标准时间
stubi.vhd
-- Generated PORTMAP Stub File: Created by Capture FPGA Flow
-- Matches PCB component pinout with simulation model
-- Created Wednesday, May 13, 2009 08:10:07 中国标准时间
platform.c
/*
* \brief Platform for Starter Kit 3A
* \author Norman Feske
* \date 2008-08-17
*/
/* FPGA includes */
#include "xparameters.h"
#include "mb_interface.h"
/* local includes */
#include "plat
platform.c
/*
* \brief Platform for ML405
* \author Norman Feske
* \author Matthias Alles
* \date 2008-08-17
*/
/* FPGA includes */
#include "xparameters.h"
#ifdef __MICROBLAZE__
#include "mb_interface.
platform.c
/*
* \brief Platform for ML507
* \author Norman Feske
* \author Matthias Alles
* \date 2008-08-17
*/
/* FPGA includes */
#include "xparameters.h"
#ifdef __MICROBLAZE__
#include "mb_interface.
netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.ngc 1140719485
OK
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
anal.out
Loading db file 'D:/Synopsys/FPGA_Express/lib/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd:
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.ngc 1140719485
OK