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readme.ml300
Xilinx ML300 platform
=====================
0. Introduction
---------------
The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
integrated AMCC PowerPC 405 core. The board is normally boo
usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
pndkr_1e_build_17.ucf
# This is a location constraints file for use with the PNDKR-1E FPGA board.
# The PNDKR-1E was designed by John Clayton
#
# Author of this file: John Clayton
# Update: Jan. 6, 2003
#
# NOTE: To
readme.ml300.svn-base
Xilinx ML300 platform
=====================
0. Introduction
---------------
The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
integrated IBM PowerPC 405 core. The board is normally boot
readme.ml300
Xilinx ML300 platform
=====================
0. Introduction
---------------
The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
integrated IBM PowerPC 405 core. The board is normally boot
mssccprj.scc
[SCC]
SCC=This is a source code control file
[FPGA串行通讯.vbp]
SCC_Project_Name=this project is not under source code control
SCC_Aux_Path=
条件赋值:使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
led.v
// Light 8 LED
// Designed By Smokingfish @ www.51FPGA.com zhiyuh@163.com
module LED (LED);
output [13:0] LED;
assign LED=14'b11100110111001;//"CP"
endmodule