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FPGA 的代码
add4in.edf
(edif Add4In
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2000 9 19 15 18 53)
(program "FPGA Express"
(version
ram_readme.txt
The following files were generated for 'ram' in directory
D:\Develop\PQS\FPGA\fft_test:
ram.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the mo
uart.vhd.txt
-------------------------------
--uart send & recive for FPGA
-- 2009
-------------------------------
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOG
uart.txt
-------------------------------
--uart send & recive for FPGA
-- 2009
-------------------------------
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOG
video.v
// FPGA PACMAN video hardware
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
module_c.edf
(edif module_c
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2003 3 26 12 11 55)
(program "FPGA Express"
(versi
module_c.edf
(edif module_c
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2003 3 26 12 11 55)
(program "FPGA Express"
(versi
module_c.edf
(edif module_c
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2003 3 26 12 11 55)
(program "FPGA Express"
(versi
module_c.edf
(edif module_c
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2003 3 26 12 11 55)
(program "FPGA Express"
(versi
module_c.edf
(edif module_c
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2003 3 26 12 11 55)
(program "FPGA Express"
(versi