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FPGA 的代码
fpga_test.ldf
/*
** LDF for adsp-BF561
**
** There are a number of configuration options that can be specified
** either by compiler flags, or by linker flags directly. The options are:
**
** USE_PROFILER0
fpga_test.h
#include
#include
#include
#include
#include
#define CLKIN (30.0e6) // clockin frequency in Hz
#define CORECLK (600.0e6)
mst_fpga.c
/*
* PXA270-based Intel Mainstone platforms.
* FPGA driver
*
* Copyright (c) 2007 by Armin Kuster or
*
*
* This c
fpga_test.ldf
/*
** LDF for adsp-BF561
**
** There are a number of configuration options that can be specified
** either by compiler flags, or by linker flags directly. The options are:
**
** USE_PROFILER0
fpga_test.h
#include
#include
#include
#include
#include
#define CLKIN (30.0e6) // clockin frequency in Hz
#define CORECLK (600.0e6)
fpga_test.ldf
/*
** LDF for adsp-BF561
**
** There are a number of configuration options that can be specified
** either by compiler flags, or by linker flags directly. The options are:
**
** USE_PROFILER0
fpga_test.h
#include
#include
#include
#include
#include
#define CLKIN (30.0e6) // clockin frequency in Hz
#define CORECLK (600.0e6)
fpga_test.h
#include
#include
#include
#include
#include
#define CLKIN (30.0e6) // clockin frequency in Hz
#define CORECLK (600.0e6)