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Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd e:\lqj\sram+fpga+usb\дsram\usb-ram\fpga/_ngo -uc ucf.ucf -p xc3s400-p

/Makefile/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /config.mk/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.c/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.h/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /quantum.c/

C:/Xilinx/ISE82/verilog/src/glbl.v C:/XUP/Markets/PLDs/Workshops/courses/v82_fpga_flow/xupv2pro/labsolutions/verilog/lab3/time_const/kcuart_rx.v C:/XUP/Markets/PLDs/Workshops/courses/v82_fpga_flow/x

C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab1/Flow_Lab/INT_TEST.VHD J:/I.27/rtf/vhdl/src/unisims/unisim_VITAL.vhd C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga

D:\fpga_work\sd_de1\DE2_CCD_CV\software\.metadata\.plugins\org.eclipse.cdt.core\481861272.index D:\fpga_work\sd_de1\DE2_CCD_CV\software\.metadata\.plugins\org.eclipse.cdt.core\3748836039.index

/Makefile/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /config.mk/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.c/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /fpga.h/1.1.1.1/Wed Apr 6 15:04:32 2005/-ko/ /quantum.c/

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -w -intstyle ise -ol std -t 1 DDR_TX_TEST_map.ncd DDR_TX_TE

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 w1131032666 FE:/farsight_fpga_course/