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# # Makefile for Etrax-specific drivers # O_TARGET := drivers.o obj-y := obj-$(CONFIG_ETRAX_VIRTEX_FPGA) += virtex.o obj-$(CONFIG_ETRAX_ETHERNET) += ethernet.o obj-$(CONFIG_ETRAX

# # Makefile for Etrax-specific drivers # O_TARGET := drivers.o obj-y := obj-$(CONFIG_ETRAX_VIRTEX_FPGA) += virtex.o obj-$(CONFIG_ETRAX_ETHERNET) += ethernet.o obj-$(CONFIG_ETRAX

vlib ./work vlog ../../rtl/cc/fpga_a_cc.v view wave add wave tb_cc.u_bfm_cc.sys_clk add wave tb_cc.u_bfm_cc.cpu_cs_cc_n add wave tb_cc.u_bfm_cc.cpu_oe_cc_n add wave tb_cc.u_bfm_cc.cpu_we_cc_n

# # Makefile for Etrax-specific drivers # O_TARGET := drivers.o obj-y := obj-$(CONFIG_ETRAX_VIRTEX_FPGA) += virtex.o obj-$(CONFIG_ETRAX_ETHERNET) += ethernet.o obj-$(CONFIG_ETRAX

MO ps2dec NULL ps2dec.v vlg7D/ps2dec.bin MO clkgen NULL clkgen.v vlg60/clkgen.bin MO fpga_40Aps2 NULL fpga_40Aps2.v vlg63/fpga_40Aps2.bin MO reset NULL reset.v vlg4B/reset.bin MO pwron NULL pwron.

--------------------------------------------------------------------- -- Filename: gh_fasm_1wp_2rp.vhd -- -- -- Description: -- FASM (FPGA and ASIC Subset Model) -- Synchronous write port,

-- File modificato da Marco Mucchino & Giovanni Schiavon per il Progetto Elettronica 2 FPGA (2007) -- Le modifiche sono segnalate ---------------------------------------------------------------

m255 13 cModel Technology dF:\EdaOk\project\PeriphDIY\uart\fpga\V0p00\testbench

SSV ADNP/ESC1 Embedded Softcore Computing Nios Softcore, Altera Cyclone FPGA Last Update: February 27, 2004 ==================================================================== This

SSV ADNP/ESC1 Embedded Softcore Computing Nios Softcore, Altera Cyclone FPGA Last Update: February 27, 2004 ==================================================================== This