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/* fpga-test.c, need insmod s3c2410-fpga.o first. author: wb date: 2005-6-13 21:05 */ #include #include #include #include

vhdl work "E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\seven_bit_reg_w_ce.vhd" vhdl work "E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\count_to_16x.vhd" vhdl work "E:\linp

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -w -intstyle ise -ol std -t 1 lvds_bist_top_map.ncd lvds_bist_to

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -f lvds_bist_top.ut lvds_bist_top.ncd s FormatS

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-ff173

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc5vfx130t-

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v source_file = 1,

create_project FPGA create_library system create_library pex_lib create_library arm add_file -library system -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/xilinx_pkg.vhd add_file

xst -intstyle ise -ifn __projnav/top.xst -ofn top.syr ngdbuild -intstyle ise -dd f:\project\videosampledesign\programme\myusbsampletest\1\fpga\fpga/_ngo -uc ucf.ucf -p xc3s400-pq208-4 top.ngc top.ng

xst -intstyle ise -ifn __projnav/top.xst -ofn top.syr ngdbuild -intstyle ise -dd f:\project\videosampledesign\programme\myusbsampletest\1\fpga\fpga/_ngo -uc ucf.ucf -p xc3s400-pq208-4 top.ngc top.ng