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FPGA 的代码
fpga_7279.vhd
--FPGA控制7279的程序
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
entity FPGA_7279 is
port (
--以下是引脚信号
CLK :IN S
fpga_7279.vhd
--FPGA控制7279的程序
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
entity FPGA_7279 is
port (
--以下是引脚信号
CLK :IN S
fpga_7279.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
agnd_fpga.1
V 51
K 296682913100 GND
|R 19:34_1-24-06
Y 4
D 0 0 20 20
Z 10
i 1
U -50 -10 10 0 3 0 NETNAME=GNDA_FPGA
U 0 -60 10 0 3 0 VOLTAGE=?V
U 0 -70 10 0 3 0 PKG_TYPE=XXXX
U 0 -80 10 0 3 0 DEVICE=GNDA
fpga-test.c
/*
fpga-test.c, need insmod s3c2410-fpga.o first.
author: wb
date: 2005-6-13 21:05
*/
#include
#include
#include
#include