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FPGA 的代码
hdllib.ref
MO lcm NULL lcm.v vlg68/lcm.bin
MO rom_32x8 NULL rom_32x8.v vlg4A/rom_32x8.bin
MO fpga_lcm NULL fpga_lcm.v vlg4D/fpga_lcm.bin
hdllib.ref
MO lcm NULL lcm.v vlg68/lcm.bin
MO rom_32x8 NULL rom_32x8.v vlg4A/rom_32x8.bin
MO fpga_lcm NULL fpga_lcm.v vlg4D/fpga_lcm.bin
cosfunc.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
cosfunc_test.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
costest.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_fpga_1280x8_tb is
generic(
SENDFILE01 : string := "uart_send_data1.dat";
idle : integer := 1;
start
cosfunc.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
cosfunc_test.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
costest.xco
# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: cos
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_fpga_1280x8_tb is
generic(
SENDFILE01 : string := "uart_send_data1.dat";
idle : integer := 1;
start