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FPGA 的代码
bibus.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
top.bld
Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
e:\study\software\fpga\fpga+usb\bulkin\fpga/_ngo -uc ucf.ucf -p xc3s4
hdllib.ref
MO diag NULL diag.v vlg61/diag.bin
MO serial NULL serial.v vlg20/serial.bin
MO fpga_40RS232 NULL fpga_40XRS232.v vlg25/fpga_40RS232.bin
hdllib.ref
MO diag NULL diag.v vlg61/diag.bin
MO serial NULL serial.v vlg20/serial.bin
MO fpga_40RS232 NULL fpga_40XRS232.v vlg25/fpga_40RS232.bin
state2.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\stratix.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
state2.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\stratix.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
complex_bibus2.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
complex_bibus.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
bibus.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
hdllib.ref
MO diag NULL diag.v vlg61/diag.bin
MO serial NULL serial.v vlg20/serial.bin
MO fpga_40RS232 NULL fpga_40XRS232.v vlg25/fpga_40RS232.bin