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FPGA 的代码
vidime.h
/*
** (c) Nallatech Ltd 2002
** www.nallatech.com
**
** 18/11/2002
**
** This is the header to the interface library for the interface FPGA to User FPGA interface core example
**
*/
#includ
vidime.h
/*
** (c) Nallatech Ltd 2002
** www.nallatech.com
**
** 18/11/2002
**
** This is the header to the interface library for the interface FPGA to User FPGA interface core example
**
*/
#includ
othertest.c
#include "wea_dos.h"
void FpgaTest(char* info)
{
unsigned short p=FPGA_TEST;
BYTE d;
strcpy(info,"FPGA PCB test:\n\r");
/* test FPGA*/
d=0xab;
outb(p,d);
DelayMs(100);
d=inb(p);
if
notgate.prj
Created by PCM: 3/4/102
Empty design C:\FPGA\NOTGATE\NOTGATE\notgate.EDF created: 3/4/102 [16.11.2].
'C:\FPGA\NOTGATE\NOTGATE\notgate.vhd' saved on 02/03/04 16:14
Document c:\fpga\notgate\notgate\n
b_lcddriver.c
#include "OMAP_MPU_Addr.h"
#include "pccdef.h"
#define FPGA_ADDRL *((volatile unsigned short *)(0x0E000000))
#define FPGA_ADDRH *((volatile unsigned short *)(0x0E000002))
#define FPGA_RDATA
fesc_5554_fspi.c
/*************************************************************************/
/* FUNCTION : general FPGA-SPI Operations */
/* PURPOSE :
vhdl1.vhd
-- Quartus VHDL Template
-- State Machine with Asynchronous Reset (1 block)
-- State Machine outputs will be registered
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vhdl1 IS
PORT
(
top_func.v
/******************************************************************************
*
* File Name: top.v
* Version: 1.0
* Date: Jan 12, 2001
*
* Description: instantiate ddr_ct
top_func.v
/******************************************************************************
*
* File Name: top.v
* Version: 1.0
* Date: Jan 12, 2001
*
* Description: instantiate ddr_ct
mainstone.h
/*
* PXA270-based Intel Mainstone platforms.
*
* Copyright (c) 2007 by Armin Kuster or
*
*
* This code is licensed