代码搜索结果

/* 用8031加载ALtera的FPGA，也可用于Xilinx的FPGA的加载 */ void load_epld(void) { unsigned char data i; unsigned int data j; unsigned char xdata * data pt; SCON = 0x0; /* 设置8031工作在方式0，

VHDL程序范例 function NCNoErr

4位乘法器,vhdl--我们的技术是您的(o4icwin & wyouken)！ www.icwin.netAD [经验代码]->[FPGA 开发经验]->4位乘法器,vhdl 4位乘法器,vhdl 4位乘法器,vhdl

F:/fpga test/mcu_sram_test/mcu_sram_test.vwf 0 6151866 777 6151866 2 F:/fpga test/mcu_sram_test/sram_control.vwf 0 1000000 859 1000000 0 F:/fpga test/mcu_sram_test/mcu_fpga_control.vwf 1328000 26560

F:/fpga test/校赛(1) 鉴相/phase_test/phase_test.vwf 49687308 51249802 671 1562494 0 F:/fpga test/校赛(1) 鉴相/phase_test/db/phase_test.sim.vwf 24999904 74999712 671 49999808 0

F:/fpga test/sram_control/db/sram_control.sim.vwf 3656 368424 748 364768 4 F:/fpga test/sram_control/sram_control.vwf 307625 807625 859 500000 59 F:/fpga test/sram_control/Waveform1.vwf 162900 33470

@N: CD630 :"D:\cpld\fpga\getpcm\pcm.vhd":6:7:6:9|Synthesizing work.pcm.art_pcm Post processing for work.pcm.art_pcm

@N: CD630 :"D:\cpld\fpga\getpcm\uartrec.vhd":6:7:6:13|Synthesizing work.uartrec.atr_uartrec Post processing for work.uartrec.atr_uartrec

@N: CD630 :"D:\cpld\fpga\getpcm\baudr.vhd":5:7:5:11|Synthesizing work.baudr.art_baudr Post processing for work.baudr.art_baudr @N: CL177 :"D:\cpld\fpga\getpcm\baudr.vhd":37:1:37:2|Sharing sequentia

-inp "getpcmdata.ncd" -dir "d:/cpld/fpga/getpcm" -prj "getpcmdata" -gui -touch ngd -par -touch tcm -lpf "getpcmdata.lpf" -prf "getpcmdata.prf" -msg "Post-PAR Design Floorplan"