代码搜索结果

m255 13 cModel Technology dJ:\计算机技术\FPGA\杜正杰FPGA\fpga_jpeg\rgb2ycrcb

E:/AJian/FPGA/LiangZhu/liangzhu.vwf 1966039142 1966117182 614 78040 0

E:/FPGA/project/ADControl/db/block1.sim.vwf 2658054 2696804 775 38750 0 E:/FPGA/project/ADControl/block1.vwf 0 1000000 20 1000 0 block1.vwf 0 100000000 20 1000 0

/***************************** file ad_control.v function : make a control bus to get value from ads807 and send it to fpga bus control with interrupt ************* clk --

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn

[General Information] 书名=CPLD/FPGA设计及应用 作者= 页数=267 SS号=0 出版日期= Vss号=61790161

有人用FPGA控制过液晶屏吗（vhdl)

vendor_name = ModelSim source_file = 1, D:/fpga例子/clk_div5/clk_div5.vhd source_file = 1, D:/fpga例子/clk_div5/clk_div5.vwf design_name = clk_div5 instance = comp, \clk~I\, clk, clk_div5, 1 instance

Record=PrintOutSet|PCBFileName=电梯FPGA.PCB|Printer=hp LaserJet 1300 PCL 6net|LeftOffset=0|BottomOffset=0|BorderSize=5000000|XCorrection=1.00|YCorrection=1.00|PrintScale=1.00|OverwriteFolders=True|CopyP