代码搜索结果

# Xilinx CORE Generator 6.3i # User = user Initializing default project... Loading plug-ins... All runtime messages will be recorded in D:\fpga\xilins2board\Example\pwm\coregen.log # lockprojectp

D:\fpga\xilins2board\Example\pwm\pwm.ngc 1145711422 OK

. clock clock.v f:\dp-fpga\实验例程\clock\clock.v

-dd f:/dp-fpga/实验例程/clock/_ngo -nt timestamp -p xc2s100-pq208-5 clock.ngc clock.ngd

. buzz buzz.v f:\dp-fpga\实验例程\buzz\buzz.v

# begin LFP file D:\fpga\xilins2board\Example\buzz\buzz.lfp designfile buzz.ngd INST "buzz" COLOR=15 ;

D:\fpga\xilins2board\Example\buzz\buzz.ngc 1145700454 OK

. dled dled.v f:\zhiyuan\dp_series\dp-fpga\dp-fpga-cd\example\7led\dled.v

D:\fpga\xilins2board\Example\7led\dled.ngc 1145701798 OK

m255 13 cModel Technology dJ:\计算机技术\FPGA\杜正杰FPGA\fpga_jpeg\rgb2ycrcb