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找到约 6,434 项符合
FPGA 的代码
wed.zsf
E:/FPGA/work/spi3310/db/spi3310.sim.vwf 0 33467741 868 33467741 0
E:/FPGA/work/spi3310/spi3310.vwf 0 37750 20 1000 0
spi3310.vwf 0 1000000 20 1000 0
E:/FPGA/work/spi3310/main.vwf 0 1000000 20 1000
alteranois问答1.txt
rzsheng问：请介绍一下你们现在的产品系列，以及大概的价位，如何？
专家答复：<mark>FPGA</mark>主要的系列是cyclone,stratix以及StratixII.
dahai_79问：nios II 开发套件主要集成了哪些外围功能？
专家答复：NIOS2 开发套件包括了存储器接口,ICP/IP, 串口,IP
fenglong问：软件平台是免费的吗？
专家答复：软件平台是免费的 ...
fpga.lst
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE FPGA
OBJECT MODULE PLACED IN .\
fpga.c
#include "extData.h"
#include "define.h"
#include "fpga.h"
#include "dvIIC.h"
#include "stdio.h"
#include "intrins.h"
//FPGA
volatile BYTE xdata CNTLGain _at_ 0x07E0;
volatile BYTE xda
pex.fes
create_project FPGA
create_library system
create_library pex_lib
create_library arm
add_file -library system -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/xilinx_pkg.vhd
add_file
coregen.log
# Xilinx CORE Generator 6.1i
# User = 刘韬
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log
# busformat=BusFormatAn
fx2_to_extsyncfifo.plg
礦ision2 Build Log
Project:
D:\FPGA\FPGA&USB\fifo_FPGA\FX2_to_extsyncFIFO.uv2
Project File Date: 03/12/2008
Output:
work__info
m255
13
cModel Technology
dD:\luoqiwu\FPGA\oytt
T_opt
Vm4>FHUWKlgW]OJ[CQ?^
fpga-driven led display.txt
FPGA驱动LED静态显示程序(1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (seg:in std_logic_vector(3 downto 0 ); --四位二
ctr.qarlog
Quartus II Archive log -- F:/work/project/circuit/FPGA/ctr/ctr.qarlog
Archive: F:/work/project/circuit/FPGA/ctr/ctr.qar
Date: Thu Sep 18 15:13:57 2008
Quartus II 7.2 Build 175 11/20/2007 SP 1 S