代码搜索：FPGA

找到约 10,000 项符合「FPGA」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/448006/7542027

prm bcd_7seg.prm

PROMGEN: Xilinx Prom Generator G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o g:\vijay_fpga_lab\bcd_7seg//bcd_7seg -u 0 G:\vijay_FPGA_LAB\bcd_7seg\bcd_7s
·
www.eeworm.com/read/447993/7542511

prm 11bit_add.prm

PROMGEN: Xilinx Prom Generator G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o g:\vijay_fpga_lab\1bit_add//11bit_add -u 0 G:\vijay_FPGA_LAB\1bit_add\bit_a
·
www.eeworm.com/read/447993/7542518

prm 1bit_add.prm

PROMGEN: Xilinx Prom Generator G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o g:\vijay_fpga_lab\1bit_add//1bit_add -u 0 G:\vijay_FPGA_LAB\1bit_add\bit_ad
·
www.eeworm.com/read/152695/5668506

h pci405.h

/* * (C) Copyright 2001 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free so
·
www.eeworm.com/read/143791/5754587

h pci405.h

/* * (C) Copyright 2001 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free so
·
www.eeworm.com/read/143791/5755289

h pci405.h

/* * (C) Copyright 2001 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free so
·
www.eeworm.com/read/155374/5624139

h pci405.h

/* * (C) Copyright 2001 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free so
·
www.eeworm.com/read/429591/8801311

h switch.h

/* FJ:SupportForTARBO-20020617-V01L01 */ #ifndef __SWITCH_H__ #define __SWITCH_H__ // ioctl cmds #define FPGA_SW_MAJOR 250 #define FPGA_SW_IOC_MAGIC 0xdc #define FPGA_SW_READ _IOR(FPGA_SW_IOC_MAGIC
·
www.eeworm.com/read/447993/7542564

log coregen.log

# Xilinx CORE Generator 6.3i # User = administrator Initializing default project... Loading plug-ins... All runtime messages will be recorded in F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_
·
www.eeworm.com/read/265938/11248907

h switch.h

/* FJ:SupportForTARBO-20020617-V01L01 */ #ifndef __SWITCH_H__ #define __SWITCH_H__ // ioctl cmds #define FPGA_SW_MAJOR 250 #define FPGA_SW_IOC_MAGIC 0xdc #define FPGA_SW_READ _IOR(FPGA_SW_IOC_MAGIC
·