代码搜索：FPGA

找到约 10,000 项符合「FPGA」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/38966/1119161

edf fpga_16bitcounter.edf

(edif FPGA_16BitCounter_PrjFpg (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2010 5 8 10 29 5) (program "Altium D
·
www.eeworm.com/read/38966/1119162

edfpreview fpga_16bitcounter.edfpreview

[Preview] LargeImageOriginalSize=708000 LargeImageWidth=354 LargeImageHeight=500 LargeImage=78DAEDDD0192E2489205D0B9591DADF7267D943ACA1CA57699316D7BFD720F09100924AFCC9E2509921064961319F115F1EBD7AF
·
www.eeworm.com/read/38966/1119171

prjfpg fpga_16bitcounter.prjfpg

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= LogFolderPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchivePr
·
www.eeworm.com/read/38966/1119181

edfpreview fpga_project1.edfpreview

[Preview] LargeImageOriginalSize=708000 LargeImageWidth=354 LargeImageHeight=500 LargeImage=78DAEDDD0B72DBC61205D0EC4C4BCBDB8997A2A578297A815313B7DADD03803F00D249D5295114097E1C354733173D1F1F1F7F7D
·
www.eeworm.com/read/38966/1119183

edf fpga_project1.edf

(edif FPGA_Project1_PrjFpg (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2010 5 27 16 1 39) (program "Altium Desi
·
www.eeworm.com/read/38966/1119187

prjfpg fpga_project1.prjfpg

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= LogFolderPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchivePr
·
www.eeworm.com/read/38966/1119188

prjfpgstructure fpga_project1.prjfpgstructure

Record=TopLevelDocument|FileName=CPU.SchDoc Record=Configuration|Name=EPM7128|DeviceName=EPM7128ELC84-20
·
www.eeworm.com/read/38966/1119196

edfpreview fpga_project1.edfpreview

[Preview] LargeImageOriginalSize=708000 LargeImageWidth=354 LargeImageHeight=500 LargeImage=78DAEDDD0B72DB48AF06D0ECCC4BCBBF932CC54BC952722F33D5098C004D524F523A5375CAB24C3D3D81DADD1FD1BF7EFDFAF60B
·
www.eeworm.com/read/38966/1119198

edf fpga_project1.edf

(edif FPGA_Project1_PrjFpg (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2010 5 27 17 29 25) (program "Altium Des
·
www.eeworm.com/read/38966/1119199

prjfpg fpga_project1.prjfpg

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= LogFolderPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchivePr
·