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fpga_dsp_portlink.psp

fpga_dsp_portlink.pin

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

fpga_dsp_portlink.fld

E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db FPGA_DSP_PortLink

fpga-design-guide.pdf

fpga-ethernet-video.pdf

fpga_eeprom_load.pdf

fpga1_drv.h

/*Physical addresses of FPGA1 registers by Xue, Zhenwu*/ /*FPGA1 registers for audio codec, Physical address*/ #define PA_FPGA1_DIVIDER 0x09000000 #define PA_PLL1700_SET_REG

fpga1_drv.o

fpga1_drv.c

/*FPGA1 driver by Xue, Zhenwu*/ #define __NO_VERSION__ #ifndef MODULE #define MODULE #endif #ifndef __KERNEL__ #define __KERNEL__ #endif #include #include

fpga1_app.c

#include #include #include #include #include #include #include #include