代码搜索结果

wave_generator.vwf 0 0 0 0 0 E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告1_函数发生/wave_generator/db/wave_generator.sim.vwf 14033742 26058278 784 12024536 0 E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/

E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/adder/db/adder.sim.vwf 0 500000 815 500000 0 E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/adder/adder.vwf 0 26149 523 26149 0 adder.vwf 0 1000000 20 1000 0 E:/2008-2008学期工作

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn

[General Information] 书名=FPGA/VHDL快速工程实践入门与提高 作者= 页数=208 SS号=0 出版日期=

;Cspa223.asm EPROM EQU 2000H FPGA EQU 8000H CTC EQU 0A000H AX EQU 1CH BX EQU 1EH CX EQU 20H DX EQU 22H PX EQU 24H QX EQU 26H IX EQU 28H HX EQU 2AH YX EQU 2CH ZX

G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/EP2C5Q208.quartus_db EP2C5Q208

m255 13 cModel Technology dE:\ying vadd_12b IDEGRUZh^]a785C>dM9F`V2 Vzn

E:/homework/fpga/top_tp.v {1 {vlog -work work E:/homework/fpga/top_tp.v Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb 2 2005 -- Compiling module top_tp Top level modules: top_tp

E:/fpga/enter_x.v {1 {vlog -work work E:/fpga/enter_x.v Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb 2 2005 -- Compiling module enter_x Top level modules: enter_x } {} {}} E:

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log # busformat=BusFormatAn