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FPGA 的代码
fpga_uartrw.map.smsg
Warning (10268): Verilog HDL information at fpga_transmitter.v(27): Always Construct contains both blocking and non-blocking assignments
fpga_uartrw.asm.rpt
Assembler report for fpga_uartrw
Wed May 07 10:10:07 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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1. L
fpga_uartrw.flow.rpt
Flow report for fpga_uartrw
Wed May 07 10:10:09 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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1. Legal
fpga_loadercfg.s62
;; Do *not* directly modify this file. It was
;; generated by the Configuration Tool; any
;; changes risk being overwritten.
;; INPUT fpga_loader.cdb
;; CONFIGURATION/VERSI
fpga_loadercfg.h62
;; Do *not* directly modify this file. It was
;; generated by the Configuration Tool; any
;; changes risk being overwritten.
;; INPUT fpga_loader.cdb
;; CONFIGURATION/VERSI
build-fpga_loader.tcf
/*
* ======== build-fpga_loader.tcf ========
*
*! Revision History
*! ================
*! 27-Jun-2003 mw Created.
*
* To create fppa_loader.cdb:
*
* 1) Open a Windows command promp
fpga_loader_ahex.cmd
debug\fpga_loader.out
-a
-memwidth 8
-boot
-bootorg 0x90000400
-bootsection .boot_load 0x90000000
ROMS
{
FLASH: org = 0x90000000, len = 0x80000, romwidth = 8, files = {fpga_loader_ahex
fpga_loadercfg_c.c
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten. */
/* INPUT fpga_loader.cdb */
/* Includ