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FPGA 的代码
fpga_lcm.v
module fpga_lcm(
DIP2K1,
// LCM ...........................................
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7,
E, RS, RW,
GCLK0
);
//*************************************
fpga_lcm.xst
set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn fpga_lcm.prj
-ifmt mixed
-ofn fpga_lcm
-ofmt NGC
-p xc2s200-5-pq208
-top fpga_lcm
-opt_mode Speed
-opt_level 1
-iuc NO
-lso fpga_lcm.lso
fpga_lcm.prj
verilog work rom_32x8.v
verilog work lcm.v
verilog work fpga_lcm.v
fpga_lcm.syr
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.30 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to
fpga_lcm.ut
-w
-g DebugBitstream:No
-g Binary:no
-g Gclkdel0:11111
-g Gclkdel1:11111
-g Gclkdel2:11111
-g Gclkdel3:11111
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:Pu
fpga_lcm.lso
work
fpga_lcm.twr
--------------------------------------------------------------------------------
Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -ints
fpga_defs.h
/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
/*
* FPGA specific definitions
*/
#ifndef __CHELSIO_FPGA_DEFS_H__
#define __CHELSIO_FPGA_DEFS_H__
#define FPGA_PCIX_A
excite_fpga.h
#ifndef EXCITE_FPGA_H_INCLUDED
#define EXCITE_FPGA_H_INCLUDED
/**
* Adress alignment of the individual FPGA bytes.
* The address arrangement of the individual bytes of the FPGA is two
* byte alig
intr_fpga.h
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you lic