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fpga_lcm.bld
Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm/_n
fpga_lcm.ucf
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "DB0" LOC = "P179" ;
NET "DB1" LOC = "P181" ;
NET "DB2" LOC = "P188" ;
NET "DB3" LOC = "P191"
fpga_lcm.xpi
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF
fpga_lcm.par
Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
TOMWANG:: Fri Feb 24 06:52:59 2006
C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_lcm_map.ncd
fpga_lc
fpga_lcm.pad
Release 6.2i - Par G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Fri Feb 24 06:53:02 2006
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft E
fpga_lcm.lfp
# begin LFP file f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm\fpga_lcm.lfp
designfile fpga_lcm.ngd
INST "fpga_lcm" COLOR=15 ;
fpga_lcm.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net lcm__n0033 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into th
fpga_lcm.mrp
Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'fpga_lcm'
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-5 -cm
area -pr b
fpga_lcm.bgn
Release 6.2i - Bitgen G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "fpga_lcm.ncd".
"fpga_lcm" is an NCD, version 2.38, d