代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/165843/10050195
v async_transmitter.v
// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module async_tran
www.eeworm.com/read/164962/10080322
vhd statmach_altera.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/164962/10080328
txt adder_nbit_generate.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/164962/10080398
txt priority_encoder_highest.txt
--Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --inputs
www.eeworm.com/read/164962/10080409
vhd counters_altera.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/163129/10174672
v 加法器源程序.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter
www.eeworm.com/read/162472/10303147
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/162469/10303214
v 加法器源程序.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter
www.eeworm.com/read/353811/10416335
txt 最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/353811/10416342
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all