代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/395023/8199437

rpt fen1250.rpt

Project Information f:\fpga 232\fen1250.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 12/21/2008 14:36:19 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/370579/9595047

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
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www.eeworm.com/read/370579/9595115

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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www.eeworm.com/read/370579/9595131

txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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www.eeworm.com/read/369385/9651542

vhd addn.vhd

-- n-bit Adder using the Generate Statement -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY addn IS GENERIC(n : POSITIVE := 3); -
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www.eeworm.com/read/369385/9652166

vhd moore1.vhd

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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www.eeworm.com/read/369385/9652313

vhd moore2.vhd

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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www.eeworm.com/read/170596/9797250

txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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www.eeworm.com/read/415351/11075476

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
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www.eeworm.com/read/415351/11075526

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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